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Error-tolerant Stream Processing System Design (ESP-SD)

New EPSRC ICT Responsive Mode grant in collaboration with the University of Edinburgh and Imagination Technologies
Error-tolerant Stream Processing System Design (ESP-SD)

image is provided courtesy of Davide Anastasia

Congratulations to Dr Yiannis Andreopoulos, Senior Lecturer in the Communication and Information Systems research group. He is the Principal Investigator on a new 3 year EPSRC funded project worth over £800k. The work will be undertaken in collaboration with Dr Vijay Nagarajan and Dr Boris Grot from the Institute of Computer Systems Architecture at the University of Edinburgh and the British technology company, Imagination Technologies.

The energy dissipation and fault rates in future CMOS integration are expected to require the abandonment of traditional system reliability in favour of approaches that control errors across the application, runtime support, and system architecture. Commercial stakeholders of stream processing applications, such as multimedia analysis & retrieval and webpage ranking systems, already feel the strain of inadequate system-level scaling and robustness under increasing user demand. While such applications can tolerate certain imprecision (errors) in their calculations, this aspect is currently not used for system scalability and resilience.

The ESP-SD project will derive theory, methods, and a prototype set of tools for scalable adjustment of computation and error-propagation in stream processing applications operating under a fault-generating computing environment. This will be achieved via the following innovations:

  • stochastic models of error tolerance in algorithms for multimedia and linked-data analytics (used in audio/video matching, semantic multimedia retrieval, webpage ranking systems, etc.);
  • new forms of accelerated error-tolerant computation within numerical stream processing libraries;
  • opportunistic designs for compiler and runtime support offering graceful resilience to runtime errors

ESP-SD aims for up to two orders of magnitude of throughput and energy scaling against conventional processing (under the same platform), with application results that are reliable in a stochastic sense. That is, all mechanisms for acceleration, energy saving and reliability in ESP-SD are geared towards minimizing the "expected" error in applications, and not the worst-case error.

We currently have a vacancy for a Research Associate for this project.