Journal Papers
§
M. Panovic and A. Demosthenous,
“Low-Voltage MOS linear transconductor/squarer
and four-quadrant multiplier for analog VLSI,” to appear in IEEE
Trans. Circuits and Systems-I.
§
M. Panovic and A. Demosthenous,
“Analogue motion estimation based upon a difference-squared cell,”
to appear in Int. J. Electronics.
§
A. Demosthenous and I. F. Triantis, “An adaptive ENG
amplifier for tripolar cuff electrodes,” IEEE
J. Solid-State Circuits, vol. 40, pp. 412-421, Feb. 2005.
§
I. F. Triantis, A. Demosthenous and N. Donaldson, “On
cuff imbalance and tripolar ENG amplifier
configurations,” IEEE Trans. Biomed.
Eng., vol. 52, pp. 314-320, Feb. 2005.
§
R. Rieger, A. Demosthenous, and J.
Taylor, “A 230-nW, 10-s Time Constant CMOS Integrator for an adaptive
nerve signal amplifier,” IEEE J. Solid-State Circuits, vol.
39, pp. 1968-1975, Nov. 2004.
§
R. Rieger, J. Taylor, E. Comi, N. Donaldson, M. Russold,
C. M. O. Mahony, J. A. McLaughlin, E. McAdams, A.
Demosthenous, and J. C. Jarvis, “Experimental tetermination
of compound A-P direction and propagation velocity from multi-electrode nerve
cuffs”, J. Medical Engineering and
Physics, vol. 26, pp. 531-534, July 2004.
§
A. Demosthenous, J. Taylor, I. Triantis, R. Rieger, and N. Donaldson, “Design of an adaptive
interference reduction system for nerve cuff electrode recording,” IEEE
Trans. Circuits and Systems-I, vol. 51, pp. 629-639, Apr. 2004.
§
R. Rieger, J. Taylor, A.
Demosthenous, N. Donaldson, and P. Langlois,
“Design of a low noise preamplifier for nerve cuff electrode
recording,” IEEE J. Solid-State Circuits, vol. 38, pp.1373-1379, August
2003.
§
A. Demosthenous and J. Taylor, “A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder,” IEEE J.
Solid-State Circuits, vol. 37, pp. 904-910, July 2002
(invited).
§
A. Demosthenous and J. Taylor, “Effects
of signal-dependant errors on the performance of switched-current Viterbi decoders,” IEEE Trans.
Circuits and Systems-I, vol. 48, pp. 1225-1228,
Oct. 2001.
§ A. Demosthenous and J. Taylor, “A very high speed replicating current comparator for use in analogue Viterbi decoders,” J. Analog Integrated Circuits and Signal Processing, vol. 27, pp. 119-128, Apr. 2001 (invited).
§
A. Demosthenous and J. Taylor, “High-speed
replicating current comparators for analog convolutional
decoders,” IEEE Trans. Circuits and Systems-II, vol.
47, pp. 1405-1412, Dec. 2000.
§
A. Demosthenous and J. Taylor, “Reduction
of effects of signal-dependent errors in current-mode analogue Viterbi decoders,” IEE Electronics Letters, vol. 35, pp. 1686-1688, Sep. 1999.
§
A. Demosthenous and J. Taylor, “Low-power CMOS and BiCMOS circuits for analog convolutional
decoders,” IEEE Trans.
Circuits and Systems-II, vol. 46, pp., 1077-1080, Aug. 1999.
§
A. Demosthenous and J. Taylor, “2.8 V
asynchronous high-speed current comparator for sequence detection
applications,” IEE Electronics
Letters, vol. 34, pp. 1714-1715, Sep. 1998.
§ A. Demosthenous, S. Smedley, and J. Taylor, “A CMOS analog winner-take-all network for large-scale applications,” IEEE Trans. Circuits and Systems-I, vol. 45, pp. 300-304, Mar. 1998.
Conference Papers
§
I. F. Triantis and A. Demosthenous, “A high-performance
adaptive ENG amplifier,” in Proc.
IEEE BioCAS 2004 Workshop, Singapore, Dec. 2004.
(invited paper)
§
O. A. Adeniran, A. Demosthenous, C.
Clifton, S. Atungsiri, and R. S. Soin,
“A CMOS low-power ADC for DVB-T and DVB-H systems,” in Proc. 2004 IEEE Int. Symposium Circuits
Systems (ISCAS’04), Vancouver, Canada, vol. 1, pp. 209-212, May 2004.
§
M. Panovic and A. Demosthenous,
“A compact block matching cell for analogue motion estimation
processors,” in Proc. 2004 IEEE
Int. Symposium Circuits Systems (ISCAS’04), Vancouver, Canada, vol.
2, pp. 229-232, May 2004.
§
M. Panovic and A. Demosthenous,
“Compact CMOS linear transconductor and
four-quadrant analogue multiplier,” in Proc. 2004 IEEE Int.
Symposium Circuits Systems (ISCAS’04), Vancouver, Canada, vol. 1, pp.
685-688, May 2004.
§
B. Tomatsopoulos and A. Demosthenous,
“A low-power, hard-decision analogue convolutional
decoder using the modified feedback decoding algorithm,” Proc. 2004 IEEE Int. Symposium Circuits Systems
(ISCAS’04), Vancouver, Canada, vol. 4, pp. 181-184, May 2004.
§
B.V. Tomatsopoulos and A.
Demosthenous, “Effects of analogue implementation errors on the modified
feedback decoding algorithm,” in Proc.
2004 EPSRC/IEEE Postgraduate Research Conf. in Electronics Photonics
Communications and Software (PREP’04), Luton,
UK, Apr. 2004.
§
M. Panovic and A. Demosthenous,
“Versatile Analogue Motion Estimator Architecture,” in Proc. 3rd IEEE Int. Symp. on Image,
Signal Processing and Analysis (ISPA’03), Rome, Italy, vol. 2, pp.
986-990, Sep. 2003.
§
R. Rieger, A. Demosthenous, and J.
Taylor, “Continuously tunable, very long time constant CMOS integrator
for a neural recording implant,” in Proc.
29th European Solid-State
Circuits Conf. (ESSCIR’03), Estoril,
Portugal, pp. 441-444, Sep. 2003
§
B. V. Tomatsopoulos and A.
Demosthenous, “Further simulation results of the modified feedback
decoding algorithm for convolutional codes,” in
Proc. 16th European Conf. on Circuit Theory and Design
(ECCTD’03), Kraków, Poland, vol. 2, pp.
357-360, Sep. 2003.
§
R. Rieger, A. Demosthenous, and J.
Taylor, “Tunable, Very-large time constant CMOS integrator for an
implantable neural recording system,” in Proc. 16th
European Conf. on Circuit Theory and Design (ECCTD’03), Kraków, Poland, vol. 3, pp. 389-392, Sep. 2003.
§
M. Panovic and A. Demosthenous,
“Effects of reduced precision on video motion
estimation,” in Proc.2003 London
Communication Symposium (LCS’03), Sep. 2003.
§
B. V. Tomatsopoulos and A.
Demosthenous, “Effects of decoding depth on the
performance of the modified feedback decoding algorithm for convolutional
codes,” in Proc. 2003 London
Communication Symposium (LCS’03), Sep. 2003.
§
M. Panovic and A. Demosthenous,
“Analogue implementation of mean square error function for use in motion
estimation,” in Proc. 2003
EPSRC/IEEE Postgraduate Research Conf. in Electronics Photonics Communications
and Software (PREP’03), Exeter, UK, Apr. 2003.
§
I. F. Triantis, A. Demosthenous, and N. Donaldson, “An
ENG amplifier for EMG cancellation and cuff imbalance removal,” in Proc. 2003 EPSRC/IEEE Postgraduate Research
Conf. in Electronics Photonics Communications and Software (PREP’03),
Exeter, UK, Apr. 2003.
§
B.V. Tomatsopoulos and A. Demosthenous, “Comparison of the
Viterbi and the modified feedback decoding algorithms
for convolutional codes,” in Proc. 2003 EPSRC/IEEE Postgraduate Research
Conf. in Electronics Photonics Communications and Software (PREP’03),
Exeter, UK, Apr. 2003.
§
I. F. Triantis, A. Demosthenous, N. Donaldson, and J. J. Struijk, “Experimental assessment of
imbalance conditions in a tripolar cuff for ENG
recordings,” in Proc. 1st
Int. IEEE EMBS Conf. on Neural Engineering, Capri, Italy, pp. 380-383,
2003.
§
I. F. Triantis, A. Demosthenous, and N. Donaldson, “Comparison
of three ENG tripolar cuff recording
configurations,” in Proc. 1st
Int. IEEE EMBS Conf. on Neural Engineering, Capri, Italy, pp. 364-367,
2003.
§
I. F. Triantis, R. Rieger, A.
Demosthenous, J. Taylor, and N. Donaldson, “ A CMOS adaptive interference
reduction system for nerve cuff electrode recording,” in Proc. 28th European Solid-State
Circuits Conf. (ESSCIRC’02), Florence, Italy, pp. 113-116, 2002.
§
A. Demosthenous and J. Taylor, “A 100Mb/s, 2.8V CMOS current-mode
analogue Viterbi decoder,” in Proc. 27th European Solid-State
Circuits Conf. (ESSCIRC’01), Villach,
Austria, pp. 248-251, 2001.
§
A. Demosthenous and J. Taylor, “Effects
of analogue ACS implementation errors on the modified feedback decoding
algorithm,” in Proc. 8th
IEEE Int. Conf. on Electronics Circuits and Systems (ICECS’01),
Malta, vol. 3, pp. 1235-1238, 2001.
§ A. Demosthenous and J. Taylor, “A 2.8V 200MHz replicating current comparator for convolutional decoders,” in Proc. 26th European Solid-State Circuits Conf. (ESSCIRC’00), Stockholm, Sweden, pp. 272-275, 2000.
§
A. Demosthenous, J. Taylor, and G.
Morrison, “An analogue approach to the design of motion
estimators for digital video encoding,” in Proc. 2000 IEEE Int. Symp. Circuits Systems
(ISCAS’00), Geneva, Switzerland, vol. 1, pp. 675-678, 2000
§
A. Demosthenous and J. Taylor, “An architecture for miniaturised low power convolutional
decoders”, in Proc. 10th
IEEE Mediterranean Electrotechnical Conf., (MELECON’00), Nicosia, Cyprus, pp.
852-855, 2000.
§
A. Demosthenous and J. Taylor, “A very high-speed BiCMOS current comparator for use in Viterbi
decoders,” in Proc. 6th
IEEE Int. Conf. on Electronics Circuits and Systems (ICECS’99), Pafos, Cyprus, vol. 2, pp. 1065-1068, 1999.
§
A. Demosthenous and J. Taylor, “A comparison of CMOS and BiCMOS add-compare-select circuits for maximum likelihood
sequence detectors,” in Proc. 6th
IEEE Int. Conf. on Electronics Circuits and Systems, (ICECS’99), Pafos, Cyprus, vol. 2, pp. 1073-1076, 1999.
§
A. Demosthenous and J. Taylor, “BiCMOS
add-compare-select units for Viterbi decoders,”
in Proc. 1998 IEEE Int. Symp. Circuits Systems (ISCAS’98), Monterey, CA,
vol. 1, pp. 209-212, 1998.
§
A. Demosthenous and J. Taylor, “A
winner-take-all network for large-scale analogue vector quantisers,”
in Proc. 1998 IEEE Int. Symp. Circuits Systems (ISCAS’98), Monterey, CA,
vol. 1, pp. 217-220, 1998.
§
A. Demosthenous C. Verdier,
and J. Taylor, “A new architecture for low power analogue convolutional decoders,” in Proc. 1997 IEEE Int. Symp. Circuits Systems
(ISCAS’97), Hong Kong, vol. 1, pp. 37-40, 1997.
§
A. Demosthenous, R. Akbari-Dilmaghani, S. Smedley, and
J. Taylor, “Enhanced modular CMOS current-mode
winner-take-all network,” in Proc. 3th IEEE Int. Conf. on Electronics Circuits and
Systems (ICECS’96), Rodos, Greece, vol. 1,
pp. 402-405, 1996.
§
A. Demosthenous and J. Taylor, “Current-mode approaches to
implementing hybrid analogue/digital Viterbi
decoders,” in Proc. 3th IEEE Int. Conf. on Electronics Circuits and
Systems (ICECS’96), Rodos, Greece, vol. 1,
pp. 33-36, 1996.
§ A. Demosthenous, J. Taylor, and S. Smedley, “A high-speed scalable CMOS winner-take-all network,” in Proc. 1996 Int. Conf. Artificial Neural Networks, Bochum, Germany, pp. 370-375, 1996.
§
C. Verdier, A. Demosthenous, J.
Taylor, and M. Wilby, “An integrated analogue convolutional decoder based on the Hamming neural
classifier,” in Proc. Neural Networks and their Applications (NEURAP),
Marseilles, France, pp. 150-155, 1996.
last updated 18 May
2005