Optical Interconnect Networks
The provision of future services in the digital economy is reliant on achieving more power efficient computers. Bandwidth improvements in electronic interconnects have only been achieved at the expense of dramatic increases in latency and power consumption. Recent advances, such as silicon photonics and polymer waveguides embedded within printed circuit boards, indicate great promise for integrating photonic network elements within the processor package. However, given the radical changes in computer design brought about by chip multiprocessors (CMP, popularly known as multi-core processors) and the fundamental differences between electronic and photonic communications, the design implications for complete computer systems are not clear. Our highly multidisciplinary work in this area is at the interface between networks, digital design and computer science.
Towards Zero Latency Photonic Switching
Photonic networks-on-chip based on silicon photonics show great promise for reducing latency and power consumption in future CMP. However, high performance CMPs use a shared memory model which generates large numbers of short messages, creating high arbitration latency overhead for photonic switching networks. We are exploring techniques which intelligently use information from the processors or memory hierarchy to predict communication in order to setup photonic circuits with reduced or eliminated arbitration latency while keeping the flexibility and reduced resource use of photonic arbitration latency. Read more…
Full System Performance and Power Modelling of Chip Multiprocessors with Photonic Interconnect
Our work seeks to understand the performance and power consumption of CMPs with photonic interconnection. We have developed optical network models for the open source and cycle accurate gem5 computer architecture simulator enabling the simulation of complete optically interconnected CMP systems from the microarchitectural up to the operating system levels. We have also developed accurate synthesisable models for the power consumption of the electronics for physical layer, network control, edge buffering and arbitration (see the resources section below).
Power Optimised Physical and Data Link Layer Protocols for Optical Transceivers
Increasingly, communication end points are moving on-chip in System-on-Chip (SoC) processors where power consumption is critical. However, the serial electronic transceivers which provide the several Tb/s of off-chip bandwidth required in high performance SoC processors are already consuming >20% of total power. Silicon photonics has been widely proposed as one of the solutions to the processor communications bottleneck and energy issues. However, our work has shown that current optical transceiver power is dominated by physical layer (PHY) and media access control layer (MAC) functions such as serialisation/deserialisation, clock recovery and line/error coding, so a simple switch from electronic to optical transceivers will not significantly reduce power consumption. Furthermore, current standards such as Ethernet transmit continuously in order to maintain receiver synchronisation which consumes unnecesary power and is incompatible with future optical switching systems. Our work is creating new PHY/MAC layers which are optimised for optically switched and power gated networks required in future systems.
Please see the webpage of Dr Philip Watts for publications and contact details.